Design Verification Engineer

Company: Viasat
Location: Tempe
Posted on: November 14, 2024

Job Description:

About us

One team. Global challenges. Infinite opportunities. At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We're looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.
What you'll do

At Viasat, you will be joining our talented and motivated team of systems engineers, design engineers, and design verification engineers developing cutting edge communications technology with a focus on high quality and time to market! As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. Over the span of a project, you may be asked to assist with design verification planning, development of test environments and test cases, hands-on debug with the design team, and ensuring quality via collection and analysis of coverage metrics.
The day-to-day

We work in a verification environment using current tools and methodologies such as UVM (Universal Verification Methodology) an emulation platform, and the UVMF (open source Siemens framework).
What you'll need

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, Computer Engineering or a related field
• 3+ years of related experience
• Strong systemverilog experience
• Strong linux experience
• Python experience and skills
• Experience creating test plans for design verification
• Agent, environment and testbench development experience
• Good debugging skills
• Git/GitHub experience
• Demonstrated ability to work well in a team environment
• Demonstrated communication skills to inform and influence peers and supervisors
  What will help you on the job
  
  
  • Experience with UVM
  • Experience with UVMF
  • Experience with horizontal and vertical reuse methodologies
  • UVM register layer experience
  • Emulator (Palladium/Veloce) experience for simulation acceleration and software development
  • Jenkins setup and maintenance knowledge
  • Strong object oriented programming background
  • Experience with design verification tools (Cadence, Synopsys, and/or Mentor) including: Regression management, coverage closure and analysis, testbench analyzer, formal tools#LI-BBS
    Salary range
    
    $99,800.00 - $147,100.00 / annually.
    For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $123,900.00- $173,400.00/ annually
    
    
    
    At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
    EEO Statement
    
    Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click .

Keywords: Viasat, Casa Adobes , Design Verification Engineer, Engineering , Tempe, Arizona